10T SRAM Computing-in-Memory Macros for Binary and Multibit MAC Operation of DNN Edge Processors

A Robust 10T SRAM Cell with Enhanced Read Operation

This paper presents a new 10T SRAM cell that has enhanced read speed along with good read and write stability. While the read access time of the proposed cell is 0.72x and 0.83x smaller as compared to the two most popular 10T SRAM cells at 500C; the read SNM is 1.16x and 1.05x higher compared to existing 10T cells. Though the read-write power of the proposed cell is higher with respect to the e...

A 45 nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation

This paper proposes a 10T bit-cell of dual-port (DP) SRAM design to improve Static Noise Margin (SNM) and solve write/read disturb issues in nano-scale CMOS technologies. In additional used the row access transistor in the bit-cell, adding Y -access MOS (column-direction access transistor) can improve dummy-read cells’ noise margin and isolate the pre-charge noise from bit-lines in synchronous ...

Sram System Design for Memory Based Computing

Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential

As process technology is scaled down, a large-capacity SRAM will be used. Its power must be lowered. The V th variation of the deep-submicron process affects the SRAM operation and its power. This paper compares the macro area, readout power, and operating frequency among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM considering the multi-media applications. The 8T...

Low Power 10T SRAM Design for Dynamic Power Reduction

The aim of paper is to get over the problem of 6T SRAM cell where it loses its reliability at low supplies due to degraded noise margins. These is done by using a 10T SRAM where the cell uses a charge sharing technique between the transistors so that SRAM could be made more rigid against the noises that can cause damage to the cell at low power supplies and along with that charge sharing betwee...